* No specific format; however, the manuscript must be written with consistency
* A list of references AT THE END of the paper
* Do not forget to cite/quote
* Papers should be between 10-15 pages
* TIMES NEW ROMAN, 12 PTS, SINGLE LINE SPACING, SINGLE COLUMN
* MUST be in Microsoft Word Format
The new advancements in the very large scale technology, there is a need for more robust and sophisticated test methods to test the increased chip complexity. Hence, manufacturing test is becoming an enabling technology that can improve the declining manufacturing yield, as well as control the production cost, which is on the rise due to the escalating volume of test data and testing times.
The Built-in- self-repair strategy (BISR) is an efficient fault coverage mechanism. Storing fault addresses more than once and repairing fault address quickly can be done using by BIAA module. In this research study we are going to explore efficient strategies and do a comparative analysis of the different strategies.
Reducing the cost of manufacturing test, while improving the test quality required higher product reliability and manufacturing yield is an important criteria in VLSI design. For certain process technologies now a days, circuit techniques or memory types, such as high-density DRAMs, testing NPSFs may be a requirement. In this research we will also focus on faults testing in DRAMâ€™s using techniques like March-based and Non-March based test algorithms.