Question 1 : In this exercise we examine in detail how an instruction is executed in a single-cycle data path. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10001100101001100000000000110000
Assume that the data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched
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The sign-extend value: 00000000000000000000000000010000
The jump’s shift-left-2 value: 0001000011000000000001000000
The ALUOp value: 00
The Instruction value: 110000
Part C
The ALU value: 2 and 16
The Add (PC + 4) value: PC and 4
The Add (Branch) value: PC + 4 and 16 x 4
Read Register 1: 2
Read Register 2: 3
Write Register: 3
Write Data: 0
RegWrite: 1
The total execution time is 9 cycles in this case.
The nops cannot be used for elimination of this type of hazard, as nops has to be fetched, ad thus, has to be used like an instruction, whereas this hazard has to be addressed by hardware detection in processor.
The change will reduce one cycle in the execution time. Hence,
Instructions executed = 4
Cycle with 5 stages = 4 + 4 = 8
Cycles with 4 stages = 3 + 4 = 7
Hence,
speed up=8/7=1.14
Instructions executed = 4
Branches executed = 1
Cycles with branch in EXE = 4 + 4 + 1 x 2 = 10
Cycles with branch in ID = 4 + 4 + 1 x 1 = 9
Hence,
speed up=10/9=1.11
Cycles with 5 stages = 130 ps
Cycles with 4 stages = 150 ps + 20 ps
Hence,
Speed up=(8×130)/(7×150)=0.99
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