Q1)In the DLX code we used base with register displacement to load the array elements into a general purpose register:

Q2)The DLX architecture is big-endian, while the Intel x86 architecture is little-endian. Consider the 16-bit (two byte) integer 0x1234. Show how how the integer would be stored in the 16 bit memory word i on each of the architectures. Each of the architectures uses a byte-addressable memory

Q3)Find the number of addressing modes in the MIPS/DLX architecture and the Intel x86 architecture and list the modes for each architecture. Which has more addressing modes? For each addressing mode, explain how the address is calculated. (Note, some of the Intel addressing modes are quite similar if not identical.)

Q4)Suppose DLX register-memory transfer (load/store) instructions take an average of 1.5 cycles per instruction, DLX ALU instruction take 1 cycle, DLX branch instructions take 2 cycles. Suppose that Intel register-memory transfer instructions require 1.5 cycles and register-register transfer instruction require 1 cycle. Intel ALU instructions require 1.5 cycles if a memory operand is used, but only 1 cycle if only register operands are used. Intel branch instructions require 2 cycles. A program in C is compiled to DLX code and to Intel code and run on each machine. On the DLX machine, 30% of the instructions are load/store, 50% are ALU, 20% are branch. On the Intel machine 15% are register-memory transfer instructions, 15% are register transfer instructions, 35% are ALU instructions with a memory operand, 15% are ALU instructions with only register operands,and 20% are branch instructions. The differences are due to the different addressing modes available to Intel ALU instructions and DLX ALU instructions. Some DLX register-memory instructions are replaced by ALU instructions with memory operations. What are the CPIs for the programs on the two architectures? Assume the cycle time on both machines is 1ns. Suppose the DLX program version runs 1,000,000 instructions. How many Intel instructions must there be in order for the execution time to be the same? What does this result mean?

Q5)Consider the arithmetic expression A=A+B*C/D+C/D+F*(A+B*E+C/D). show how to implement the expression in DLX and Intel x86 assembly code. Use the normal arithmetic evaluation order and precedences when implementing the expression

Q6)Write a short DLX assembly program that adds together an array of five integers:

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