For the op amp circuit below:
Figure 1: Op Amp Circuit.
(a) Showing all working, derive the transfer function Vo/Vin in the s-domain.
(b) Using your customised value of f1, choose values of C1 and C2 so that the 3dB frequency of
both poles = f1 Hz. Use R1 = 50kâ„¦, R2 = 100kâ„¦, R3 = 33kâ„¦ and power supply voltages of
(c) Use Matlab to generate the Bode plot, pole-zero diagram and transient response of your
(d) Simulate the circuit using OrCAD PSpice, and generate the transient and frequency
(e) Compare your transient and frequency responses obtained above, and comment on the
relevant parameters discussed in lectures. 2
2. Waveform Generator
For the op amp waveform generator circuit below:
Figure 2: Waveform Generator.
(a) Using your customised value of f1, choose C1 so that the frequency of the generated
waveforms = f1 Hz. Use R1 = 22kâ„¦, R2 = 68kâ„¦, R3 = 100kâ„¦, R4 = 100kâ„¦, R5 = 50kâ„¦, R6 =
100kâ„¦, R7 = 33kâ„¦, C2 = 500nF, and power supply voltages of ±5V. For C3 and C4, use your
values of C1 and C3 from (1).
(b) Simulate the circuit using PSpice, and plot the waveforms at V1, V2, and Vo. Make sure you
run the simulation for long enough so that V2 settles to a stable waveform. Comment on your
ASSIGNMENT PART B
3. Data transfer problem – filter design and simulation
A computer system is transferring data serially on a single wire at a rate of B bits per second. The
sequence of bits alternates between “high’ and ‘low’ values as shown in the waveform in Figure
B1. There is source of 100 KHz noise in the environment, which is corrupting the data. It is
necessary to filter out the noise without destroying the data waveform such that a detector at the
receiver can still decide ‘high’ and ‘low’ values correctly and receive the correct sequence of bits.
A filter circuit as shown in Figure B2 is considered for this purpose. Your task is to analyse the
circuit, design it for the right component values and simulate it to view the input and output
waveforms. You will evaluate two scenarios: (a) B = 1000 bits/sec and (b) B = 25000 bits/sec.
Figure B1: Digital data waveform.
Figure B2: Active filter circuit. 4
(a) Showing all working, find the transfer function Vout/Vin of this circuit in terms of R1, R2, R3, C1
and C2, using nodal analysis in the s domain.
(b) Write down the characteristic equation for this system and formulae for the natural frequency
and the damping ratio in terms of component values. Write down the locations of the poles in
terms of the natural frequency and the damping ratio. Make the simplifying assumption that R
= R1 = R2 = R3
(c) By placing at least one pole well below the frequency of the noise source, the gain of the filter
will be small at the frequency of the noise source and it will be effectively filtered out. Select an
overdamped system with natural frequency of 25Krad/sec and damping ratio 2 to achieve this.
Determine the locations of the poles and sketch the pole-zero plot. Using your customised
value of R (kâ„¦), find the capacitor values for this design.
(d) Enter your transfer function into Matlab, and use Matlab to generate the Bode plot and polezero
(e) Simulate your circuit using PSPICE and a simplified Op Amp model with a voltage dependent
voltage source with input resistance 1Mohms, Gain 100,000 and output resistance 50 ohms.
Use a sinusoidal source as the noise source with amplitude 2V. Plot the input and output
waveforms for data rate B = 1000 bits/sec.
(f) Now change the data rate to B = 25,000 bits/sec and perform the simulation again. Plot the
input and output waveforms. Is the data information still available and will it be correctly
(g) For a 5V step input to the filter (assuming that the gain is some constant K), perform a partial
fraction expansion and Laplace inverse to find the step response in the time domain. Identify
the time constants associated with the exponential terms in the response. Assuming that the
settling time is 5 times the time constant, calculate the settling time associated with each
exponential term (or corresponding pole). Which pole determines the settling time? How does
this compare with the time interval occupied by one bit at the data rate of 25,000 bits per
second? Which pole should be moved to decrease the settling time and in which direction?
(h) Now design a critically damped system with natural frequency of 125 Krad/sec. Find the
capacitor values required for your value of R (kâ„¦) to achieve this. Simulate your circuit and
plot the input and output waveforms for the data rate of B = 25,000 bits/sec. Will the bits be
recovered correctly? Comment.
Deliverables and Assessment
Reports should be submitted for Parts A and B showing all relevant calculations, derivations, relevant
screen captures with annotations, discussion of observations and results, and appropriate
conclusions. Assessment will be applied using Criteria Based Assessment (CRA). The CRA sheets
are available on Blackboard. The reports are to be submitted through Assignment Minder.
Jasmine Banks and Vinod Chandran