QUESTION 1 Considering the two-stage amplifier circuit below :
a) In what configuration are transistors Q2 and Q3 connected? (5 marks)
b) Determine whether the biasing is such that the quiescent emitter voltage of Q2 (VEQ2) is
correctly at 0V.
c) For an input signal of 10kHz, assuming that the capacitor impedance may be considered to be very small (  0), determine the input and output resistance of your amplifier.
d) Determine the overall signal voltage gain of the amplifier, from I/P to O/P, in dB, for a signal of 10kHz with the load RL connected.
QUESTION 2 Considering the circuit diagram above in Question 1:
a) For what Class of operation is the output stage, Q2 and Q3, biased, and why?
b) Determine the maximum output voltage signal possible of the amplifier with the output load RL
connected without distortion.
c) If a capacitor of 1uF was connected in parallel with the R4 resistor (emitter of Q1), describe how
the gain of the amplifier would be effected? Calculate the new gain. (15 marks)
d) If transistors Q2 and Q3 had explain the effect on the gain, input and output
resistance of the amplifier. Consider for both cases of with or without the capacitor bypass of R4 mentioned in c).

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