There is a need to design a synthesizable Verilog code for A Mini Stereo Digital Audio Processor. The paper is attached below. Actually the midterm project is a sequence of 4 homework’s. Have attached the 4 homework’s as well. The 1st two homework’s give us idea about the algorithm of the paper and last two give us idea about the FSM using which the chip works. For homework 5 we check the FSM is showing us correct state transitions or not and in homework 6 we needed to do the computation of a single channel input. We did a Verilog code for both the homework’s which I am also attaching here. For homework 6 we couldn’t write the output file. For these two homework TA provided us data1.in and data1.out. These two files check our output is right or wrong. And using data2.in we need to generate the output file for Ta. So basically for this midterm we need to merge homework 5 and 6 and make the computation for two channels to get the output. I have also attached the requirement for the midterm spec. file here. So please read all the files carefully and we need to get a synthesizable Verilog code with proper waveforms of our state transitions and proof of showing that the code is reading all the input files and writing the output files. Just follow our homework 5 and 6 report where we have shown the waveforms and required input, output data. But now we are unable to merge them to make it for two channels. For further queries please let me know.