In this project you will create a simple 8?bit system capable of performing a similar cyphertask. You will be provided with a simple test program to evaluate the operation of your CPU
Develop an 8?bit single or multi?cycle CPU to perform a simple rotor based cipher task.
This topic has covered both the design and implementation of computer architecture. In the final project all these parts will be brought together to produce a full CPU design. This CPU will be an 8?bit design based on a subset of the MIPS instruction set using your choice of either a single?cycle or multi? cycle implementation. The basic structure of the CPU should follow the design shown in chapter three of your Computer Organisation notes. A multi?cycle machine should include a finite state machine corresponding to the five states shown on page 4 of chapter 3.
The instruction set is a based on the MIPS instruction set. You are required to implement R, I and J format instructions to the specifications shown in appendices 1 and 2. Note that all memory access including instruction fetch is 20?bit wide and performed on 20?bit boundaries. The program counter will treat each twenty?bit instruction as a single location.
Unlike MIPS this design will use Harvard architecture with separate program and data memories. You should create three memory units matching the following specifications:
Instruction memory unit –A single read port memory 1024 20 bit locations in size. All access will be on 20?bit boundaries(ROM)
Single read port – single write port memory (RAM) that can store up to 128 bytes accessed on 8?bit boundaries.
Memory mapped IO – 128 bytes on 8?bit boundaries. This represents a series of registers that are implemented externally to the CPU but share the same address bus, read, and write ports as the RAM module. A write enable signal and a multiplexor should be configured such that addresses 0 to 127 refer to RAM, while 128 to 255 refer to the external IO. Your CPU component should include ports connecting these signals to a toplevel component, but the IO registers themselves do not need to be implemented.Dual read port – single write port, 8?bit wide register bank containing 8 registers.
The ALU will be an 8?bit design based on the one developed in Practical 2.
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