ITC 544 Computer Organisation And Architecture

• Course Code: ITC544
• University: Charles Sturt University
• Country: Australia

Question:

1. Suppose that a 256M * 128 Memory built using 1024 K *32 RAM Chips and memory is word addressable.
1. How many RAM Chips are necessary
2. How many RAM Chips are there per memory word
3. How many address bits are needed for each RAM Chip
4. How many banks will this memory have
5. How many address bits are needed for all memory
6.  A digital computer has a memory unit with 48 bits per word. The instruction set consists of 240 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory.
7. How many bits are needed for the opcode
8. How many bits are needed to specify the register How many bits are left for the address part of the instruction
9. What is the largest unsigned binary number that can be accommodated in one word of memory
10. Consider an instruction Add 1000. Memory contents, Accumulator (AC), and R1 Register contents are depicted in the below figure: (such as memory address 1000 contains a value 1400, memory address 1100 contains a value 400 etc. All the numbers used here are decimals.)

Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator (AC) using the following addressing modes:

1. i)      Immediate
2. ii)     Direct

iii)    Indirect

1. iv)   Indexed
2. Write code to implement the expression: A= (B + C) * (D - E) on 2-, 1- and 0-address machines. In accordance with programming language practice, computing the expression should not change the values of its operands.

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