Metal Oxide Semiconductor Field Effect Transistor and Complementary Metal Oxide Semiconductor are two most efficient technologies for constructing the integrated circuit (Avci et al. 2013). Most of the industries are using these technologies for developing the integrated circuits.
The following assignment is done to highlight the effectiveness MOSFET/CMOS technologies in the present scenario. The comparison is being presented in this assignment among three articles regarding MOSFET/CMOS technology and logic design.
This paper is reviewing the improvisations associated with biaxial tensile stress in Si and p-MOSFETs. The high channel doping in strained silicon enhances the electron mobility. This aspect is characterized in strained silicon n-MOSFET in this paper (Hoyt et al. (2002).
The mobility in the channel dopants is induced by lowering of the carrier concentration in the inversion layer. It results into the reduction in strain- induced mobility enhancement. However, the enhancement is recovered at the high inversion charge concentration (Avci et al. 2013). There are several processes of integration challenges and opportunities associated with strained silicon n-MOSFET technology. This can be explained using dopant diffusion and the huge impact in strained Si CMOS structure.
The mobility of the carriers within the inversion layer in Si-MOSFET is used as physical element to define the drain current. This aspect is utilized to study the 2- dimensional carrier system. The electron and hole mobility follows the universal curve at the room temperature in the inversion layer that is independent of the biased substrate (Tanaka et al. 2016). In the week region of the inversion layer Coulomb scattering dominates the other carriers. Increase in the effective normal field causes the effective scattering of acoustic phonon to govern the mobility. High value of effective normal field causes the increase in surface roughness scattering and phonon smattering. Therefore, high doping in channel is needed to regulate the threshold voltage.
The mobility enhancement of the channel carriers are done at high channel doping. The strain induced on the electro mobility of Si- MOSFETs is totally dependent on the sub band structure of the channel.
The difficulties faced for scaling of the planner CMOS transistors, a considerable control in gate to channel region introduces the FINEET technology (Liu and Peide 2012). This article is elaborating the working principle, application sectors and challenges of the FINEET technologies. The effectiveness of the FINEET is it is self aligned, double-gate and comprised of CMOS circuits (Jurczak et al. 2016).
FINEET technology uses a huge part of the conventional CMOS fabrication process. The gate in FINEET requires tighter control of process rather than other planner counterpart. 20 nm width of the gate provides low threshold voltage to the circuit. As the channel is entirely depleted, the threshold voltage is limited to the gate work function (Tanaka et al. 2016). The FINEET is basically fabricated on the substrates and the vertical sidewalls of the posses and orientation about (110)/. P- Type MOSFET generally shows the higher performance as it has effective hole mobility enhancement characteristics (Jin et al. 2016). Effective drive current can be achieved by the mobility boost up are necessary.
The FINEET access resistance provides damaging impact on the high speed operations. This aspect creates problems during the formation of 3-D junctions. Small change in the implantation angle changes the implanted dose involved in the fin processing.
Low power CMOS digital design technology provides the motivational aspect to the technological development regarding the emerged battery operated an application that introduces the demands of portable environments (Avci et al. 2013). This aspect reduces the power consumption in the CMOS circuits. This article shows the circuits which utilizes low power consumptions. In this article the architectural framework is presented which shows the elements which introduce low power consumption in the system (Chandrakasan et al. 1992).
The low power consumption in CMOS digital logic design is divided into three parts mainly: static, dynamic, and short circuit power intake. Switching of power comprises both the dynamic and short circuit power (Jin et al. 2016). This aspect introduces into the system when the signals passes through the CMOS circuits and make change in the logic states of the gates (Liu and Peide 2012). This results into the charging and discharging of the load capacitors in the circuit. The static control is introduced when the transistor is in the stable logic state but it started to leak an amount of power in all junctions due to several effects. This introduces the leakage power in the circuit.
Low- power consumption in CMOS design provides power consumption. This technology block the wastage of power.
Strained silicon MOSFET technology, CMOS digital design technology and FINEET technology are three most effective technologies utilized in the modern scenario. But the low power consumption issue made the CMOS digital design technology most effective and it will technologically exists over next five years. According to the technological features, FINEET is not useful in most of the cases as it possess high power consumption and high doping concentration in the inversion layer.
Avci, U.E., Morris, D.H., Hasan, S., Kotlyar, R., Kim, R., Rios, R., Nikonov, D.E. and Young, I.A., 2013, December. Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at L g= 13nm, including P-TFET and variation considerations. In 2013 IEEE International Electron Devices Meeting (pp. 33-4). IEEE.
Barraud, S., Berthome, M., Coquand, R., Casse, M., Ernst, T., Samson, M.P., Perreau, P., Bourdelle, K.K., Faynot, O. and Poiroux, T., 2012. Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm.IEEE Electron Device Letters, 33(9), pp.1225-1227.
Chandrakasan, A., Sheng,, S. and Brodersen,, R. (1992). Low-Power CMOS Digital Design. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 27(4), pp.473-484.
Chen, Z., Yao, Y., Boroyevich, D., Ngo, K.D., Mattavelli, P. and Rajashekara, K., 2014. A 1200-V, 60-A SiC MOSFET multichip phase-leg module for high-temperature, high-frequency applications. IEEE Transactions on Power Electronics, 29(5), pp.2307-2320.
Hänsch, W., 2012. The drift diffusion equation and its applications in MOSFET modeling. Springer Science & Business Media, pp- 40-60.
Hoyt, J., Nayfeh, H., Eguchi, S., Aberg, I., Xia, G., Drake, T., Fitzgerald, E. and Antoniadis, D. (2002). Strained silicon MOSFET technology. IEEE, pp.23-26.
Jin, L., Norrga, S. and Wallmark, O., 2016, May. Analysis of power losses in power MOSFET based stacked polyphase bridges converters. In 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia) (pp. 3050-3055). IEEE.
Jurczak, M., Collaert, N., Veloso, A., Hoffmann, T. and Biesemans, S. (2016). Review of FINFET technology. IEEE.
Liu, H. and Peide, D.Y., 2012. Dual-gate MOSFET with atomic-layer-deposited as top-gate dielectric. IEEE Electron Device Letters, 33(4), pp.546-548.
Scrimizzi, F., Bazzano, G., Cavallaro, D., Comola, M., Consentino, G., Fortuna, S., Longo, G. and Pignataro, G., 2016. New LV Wide SOA Power MOSFET technology for Linear Mode operation. PCIM Europe 2016.
Tanaka, C., Matsuzawa, K., Miyata, T., Adachi, K. and Hokazono, A., 2016, January. Investigation of BSIM4 parameter extraction and characterization for Multi Gate Oxide-Dual Work Function (MGO-DWF)-MOSFET. In 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) (pp. 96-99). IEEE.
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