1. Enhanced memory reliability against multiple cell upsets using decimal matrix code.
2. Fault secure encoder and decoder for nanoMemory applications.
In the contemporary time the enhancing the capability of memory has become very crucial for every usage, as technological demands are getting increased day by day. There are several technological advancements that are being implemented into the systems for increasing the usability of the memory.
In this report two papers are getting reviewed for understanding impact of enhancing of memory utility.
1: Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code
Contemporary time is facing multiple cell upsets as one of the major issues. This is related to reliability of memories exposed in front of radiation. Prevention of MCU (Multiple Cell Upsets) is controlled by “complex error code correction (ECCs)”. In addition to this, Hamming codes that are called Matrix codes are introduced into the system for providing protection to the memory. Core issues related with this concept is that these codes are nothing but the doubled error correction code and in many cases these doubled codes cannot improve the capability of the code. In the proposed schemes of DMCs it is clear that it offers minimum circuit area by reusing encoders. This condition is mainly known as ERT that reduces ‘area overhead’. Decimal algorithms are utilized for obtaining maximum capability for detection of error code from DMC. ERT system utilizes DMC encoder as a part of decoder. Proposed DMC are compared generally with the following codes: Punctured different set (PDS), existing Hamming code and MCs. According to the measures taken for testing the usability of codes it was found that “mean time failure (MTTF) regarding proposed scheme is around 122.6%, 154.6% and 452.9%”. In addition to this, delay overhead involved in this case is decided to set at the following levels: 26.2%, 69% and 73.1%. MTBF is nothing but a measure of the reliability of some components or products. These percentages are related to following codes: MCs, Hamming codes and PDS.
Motivational goals: Following are the motivational goals of this paper:
- To increase the reliability of memory by utilizing Decimal matrix code.
- To prevent the MCU from data corruption and more complex error formation.
- To establish the memory protection through the hamming code and matrix code.
- To enhance the maximum error detection capability.
- To reduce the mean time to failure (MTTF)
2: Fault Secure Encoder and Decoder for NanoMemory Applications
This article is focusing on the enhancement of memory utility. In case of the logic circuits, the soft error rate gets increased. In addition to this, the decoder and encoders around the memory bocks behaves susceptibly towards the soft errors. Better memory protection can be obtained by the help of introducing a new system that is known as fault- secure decoder and encoder. Key part of this paper comes from indentifying new technological advancement for “error correcting codes” that makes the design of “faulty- secure detectors” simple by its redundancy. There are transient errors that specified by protecting the encoders and decoders. In this paper it has been elaborated that “EG- LDPC codes” is capable of providing “fault- security”. The EG- LDPC codes have the tolerance for protecting the encoder and decodes from system failure rates involved in the coding system. These codes can detect 10% faulty rates within the range of 10^(-18) upsets/device/cycle. Larger EG- LDPC codes can provide lower area of overhead and helps to gain higher reliability in the field of evaluation of codes. There are several benefits offered by these applications. The Nanoscale devices may not be last for long time though the efficiency provided by these devices are enough to utilize their impacts. This paper is reviewing about the fault- tolerant nanoscale architecture that specifies the transient faults within the system. In this case the supporting logic circuits are: encoders, detectors, decoders etc. In this paper this description is totally based on EG- LDPC codes.
Motivational goals: following are the motivational goals of this paper:
- To decrease the soft errors in circuits.
- To make sure about the protection of encoders and decoders in circuit.
- To increase the reliability of the memory.
- To utilize the FIT in increasing memory reliability.
- To make the design of fault- secure detector more safe and simple for utilizing it in memory design.
- To use EG- LDPC codes for reducing nano-wire defect rate.
Utilization of memory is one of the most efficient technological advancement in contemporary times. Among all of resolution processes two are discussed in this review with the help of two article review. These articles are elaborating about the following techniques: use of decimal matrix code for increasing reliability of memory and “Fault Secure Encoder and Decoder for NanoMemory Applications”. These two aspects are two ways of increasing the reliability and reusability of memory that will in terms increase the capability of the memory.
Naeimi, Helia and André DeHon. Fault Secure Encoder and Decoder for NanoMemory Applications(2009).
Guo, Jing, Liyi Xiao, Zhigang Mao, and Qiang Zhao. "Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code". IEEE (2013).
JUN, Hoyoon and Yongsurk LEE. "Protection Of On-Chip Memory Systems Against Multiple Cell Upsets Using Double-Adjacent Error Correction Codes". IEICE Transactions on ElectronicsE98.C, no. 3 (2015): 267-274.
Jiao, Jiajia, Yuzhuo Fu, and Shijie Wen. "Accelerated Assessment Of Fine-Grain AVF In Noc Using A Multi-Cell Upsets Considered Fault Injection". Microelectronics Reliability 54, no. 11 (2014): 2629-2640.
Kapileswar, N. "Fault Secure Encoder And Decoder With Clock Gating". International Journal of VLSI Design & Communication Systems 3, no. 2 (2012): 133-141.
Mathur, Nehul and Sunil Sharma. "Simulation Of Convolutional Encoder And Viterbi Decoder Using Verilog". International Journal of Computer Applications 102, no. 4 (2014): 31-34.
Sribala, Gade, D.V.N. Sukanya, K. Gouthami, and Tai-hoon Kim. "LDPC Encoder And Decoder Architecture For Coding 3-Bit Message Vector". IJSIA 9, no. 10 (2015): 21-30.
Qi, Chunhua, Li Xiao, Tianqi Wang, Jie Li, and Linzhe Li. "A Highly Reliable Memory Cell Design Combined With Layout-Level Approach To Tolerant Single Event Upsets". IEEE Transactions on Device and Materials Reliability (2016): 1-1.