Finite State Machine Design Coursework

The module learning outcomes that are assessed by this coursework are:

1. “Knowledge and specialist analytic development techniques in the areas of VLSI design, ASM design and implementation, and VHDL design.”
2. “Development of generic and transferable skills in advanced digital system design methodologies using industry standard design tools.”

Why is all the code formatted on a black background which makes it a lot less legible and far more difficult to read than normal? You were warned about this and about legibility issues in general in the first assignment. Overall 5 marks have been deducted from the total because of this.

Why does the FSM have an additional output port called Y?

When using multiple processes, each process should have a unique label.

It would be better to use relative time statements rather than using absolute time statements in the TB, i.e. it is better to use wait for clk='0' and clk'event statements rather than wait for 100ns type statements.

Discussion on the Finite state machine design

At the beginning, reset is 1 clock begins and the output is for t u v indicating state start_st. After 100 ns reset changes to 0 and input a goes high. The output at this point goes to indicating a transition to state task1.

At 200 ns, input b goes HIGH and reset remains and output goes to indicating a transition to state task2. At 300 ns input c goes LOW, reset remains and output goes to indicating a transition to state termin.

At 400 ns, input c goes HIGH, reset remains 0 and output goes to indicating a transition to state start_st. At 500 ns input b goes HIGH, reset remains 0 and output goes toindicating a transition to state task2.

At 600 ns, input c is still HIGH, reset remains 0 and output goes to indicating a transition to state task1. At 700 ns input b is still HIGH, reset remains 0 and output goes to indicating a transition to state task2.

At 820 ns, input c is goes LOW, reset remains and output goes to indicating a transition to state termin. This completes the implementation of state diagram shown given in the problem statement.

The assumption made at the design level assume the effect of prior input values of b remaining at 1 and a remaining 1 cause the series of changes of state between 420 ns and 800ns which change the value of output t according to the state diagram and the reading, for convenience purposes, is taken at 820 ns since signals a and b maintain their initial values as they do not change. The transition however still follow the state diagrams architecture.