KD7066 Analogue Electronic Design
Question:
Learning outcomes on the Module Descriptor:
1. Pertinent design knowledge from relevant research for complex analogue abstractions.
2. Critically evaluate advanced design concepts for the design of analogue circuits, at pertinent abstraction levels.
3. Demonstrate expertise in the use of industry standard CAD tools for the design, testing and modelling of innovative analogue circuitry.
4. Evaluate a design for a relevant audience in the context of professional, & commercial standards. Specific interpretation of the Learning Outcomes with respect to this laboratory examination.
This design focussed examination is based on the Cadence OrCAD software. The examination is a problem-based assessment talking the application of knowledge and understanding to both the design process and the practical skills of CAD tool usage. Critical comparison of circuit topologies will be performed using the CAD tool and an advanced use of simulation.
Design the Beta helper current mirror, shown in Figure Q1; formed from the NPN transistors Q1, Q2, Q3 and Q4, and resistors Rref, Rdeg1, Reg2 and Rdeg3.
Please make no adjustments to the resistors RLoad1 and Rload2 these are simply load resistors applied to current mirror outputs.
The following specification is to be achieved:
• Supply Voltage = +/- 9V (dual rail current mirror therefore 18V)
• Ireference (ICQ1) = 1mA
• Effective Early Voltage = 10*VAF
• Ioutput (ICQ3, ICQ4) = 2mA
Make clear your equations and calculated values of resistors Rref, Rdeg1, Rdeg2, Rdeg3.
Make clear your optimised values after simulation.
Explain why the Beta helper current mirror is used in designs so often, what are the key advantages of this design compared to a basic mirror with no beta helper transistor. You may think about counting base currents to demonstrate your explanation.
Using your design of current mirror from Q1; you are to assess the performance of your current mirror against Temperature. Use the temperature range from 0 to 100 ºC to assess the performance of the Current Mirror design.
Simulate the circuit:
• How does the Reference current (ICQ1) move with temperature?
• How the Voltage labelled VRef move with temperature?
• Ensure your simulation works correctly adjusting RelTol in advanced options as necessary.
Explain (where appropriate using equations) how temperature has affected the design of the current mirror reference current, output current and the voltage reference voltage Vref.
Q3 Design a differential amplifier, and implement two of them in place of the resistors RLOAD1 and RLOAD 2 in the current source from Q1. The specification of the differential amplifiers are the same and listed below:
• Supply Voltage +/- 9V (Dual supply rail),
• Tail currents ICQ3 and ICQ4 = 2mA (from Q1),
• ADM = 100 differential gain for both amplifiers,
• Vin Differential 10mV @ 1kHz (VinA, VinB),
• Vin Common 1000mV @ 1 kHz (VinC),
• Differential 1 replaces RLOAD1 and will measure ACM,
• Differential 2 replaces RLAOD2 and will measure ADM.
Make clear your design equations for the values of RC1, RC2, RC3 and RC4 using the small signal equivalent model to derive the gain equation for ADM. All the resistors will have the same value as this is a balanced design.
Determine the value of gain ADM from simulation and then optimise the values for all RC resistors to ensure a precise ADM gain value of 100.
Explain the limitation of the output signal swing from this design in relation to the power supply provided (dual rail +/-9V). What would have been a better design structure for this type of gain requirement?
The design constructed in Q3 is now to be considered a testbed for you to measure the performance of the differential amplifier, with respect to Common Mode
Rejection Ratio (CMRR).
Using Differential 1 designed to a ADM value of 100.
Measure this in simulation and prove this is correct.
Using Differential 2 designed to an ADM value of 100; Measure the value of ACM. Use simulation to determine the value of ACM; The input signal for VinC was set to 1000mV and therefore you should have a good clear signal at the output (VoutC) but may need to adjust RelTol in simulation advanced options, to gain a clear simulation free of simulation noise.
Determine the common mode rejection ratio for this design based on the simulation results you have just obtained. Express the value in both linear and dB terms.
Compare these values with those you know off from other operational amplifiers and comment on the performance.
The design constructed in Q3 is now to be considered a testbed for you to measure the performance of the differential amplifier with respect to Temperature, and Common Mode Rejection Ratio.
You are to simulate the circuit between temperatures 0 to 100 ºC, to determine the effects that temperature has on:
• IRef (the reference current, as in Q2)
• ITail (the current in the tail position of differential 1 and 2)
• ADM (how does the differential gain move, if at all?)
• ACM (how does the common mode gain move, if at all?)
• CMRR (is this effected by Temperature)
Explain your results and thinking from the data you have obtained. You should be thinking about how you can redesign the circuit to improve any issues you have found.
