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Logic Design Assignment

Boolean Functions Simplification

in PDF. Be sure to follow all assignment expectations. Show your work in detail, and explain your process / reasoning. It is likely you will be able to find solutions for these questions online. Any similarity to online solutions, or other student solutions (current or past) will be identified and reported. Question 1: Simplify the following expressions to the given criteria (a) G(A,B,C) = (((A+C)B')+A')' to fewest logic levels (b) F(X,Y,Z) = XY+XY'+X'YZ using only NAND gates Question 2: (a) Simplify the Boolean function F together with the don’t care conditions d in sum of products form. Indicate all essential prime implicants, and state which remaining prime implicant(s) you selected. F(w,x,y,z) = ?m(0,1,3,7,9,10,13); d(w,x,y,z) = ?m(2,4,8,15) You may use the template “k-map-4.xls” provided on urcourses. You do not have to draw the circuit. (b) Simplify the above Boolean function (with don't cares) using product of sums, with Maxterms, instead of sum of products with minterms. (c) Convert the product of sums from part (b) into sum of products form using Boolean simplification. Is this equivalent to what you found in part (a)? Should it be? Why or why not? Question 3: Design a combinational circuit with 4 inputs, A3, A2, A1, A0; and three outputs, X, Y, Z. The inputs represent a binary number in the range [0..15], and the outputs represent characteristics of the numbers. Specifically, X should be true if the number is divisible by 3; Y should be true if the number is prime; and Z should be true if the number is a power of 2. As an example, if the input is A3A2A1A0= 1100, this represents the number 12, which is divisible by 3, not prime, and not a power of 2 so the outputs should be XYZ =100. Recall that 0 is divisible by any integer. (a) Implement the circuit with AND gates, OR gates, and NOT gates. inverted inputs are OK. You may use the k-map template provided for your design work. You may use inverted inputs on gates. (b) Implement the circuit using AND, OR, NOT, and XOR gates. How much simpler is this design than the design in part (a)?

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