Design and Simulation of Error Correcting Code using Quartus II Simulation Tool

The students use the logic simulation Quartus II tool to simulate the operations of a single error correcting code.After designing and testing the encoder and decoder the students experiment with all possible multiplicity andcombination of channel introduced errors and assess the usefulness of the codec in terms of the average error

per data transmitted bit

After the assessment the students should have a clearview of

1. the operation of a codec in communicationsystems

2. the capabilities and restrictions of linear blockHamming codes

3. the design issues involved in the encoder anddecoder stage of an error control codec

4. the basic functionality offered by the Quartus IIsimulation tool

1. Describe the aims, objectives and scope of theassignment

2. write a small introduction on the theoryunderlying the linear block Hamming codes

3. Design and simulate the encoder

4. Design and simulate the decoder

5. explain the design of the decoder

6. Tabulate the results of simulating the operationof the codec, based on all possibletransmission errors

7. Explain anomalies and justify results

8. Compare the performance of the codec withthe uncoded caseAssessment method by which a student can demonstrate learning outcomes:

1. Design Encoder, describe implementation and simulate circuit to check correct operation; (8%)

2. Design Decoder, describe implementation and simulate circuit to check correct operation (12%)

3. Combine Encoder - Decoder with error introduction, describe implementation and simulate (check)circuit for single errors (16%)

4. Use Codec to examine the effect for additional errors – Run simulations and explain results (20%)

5. Calculate post codec probability of a code being in error,overall average number of errors per 6bit word,plot decoded error probability, find the useful range of channel bit error probability and discussoutcome (24%)

6. Produce a well structured, engineering level report with conclusions (20%) Draw conclusions on the usefulness of the codec

In this assignment you are going to design, implement and test the performance of a simple error control codec (ENCODER – DECODER). The logic design will be based on QUARTUS® II, which is a design tool for programmable logic devices. You will use the system to design the logic for an encoder, a decoder and then combine the two with inputs to introduce errors into the transmission bits. The exercise will be given in short form and structured as a tutorial exercise for learning QUARTUS® II.

After the assessment the students should have a clear view of

1. the operation of a codec in communication systems

2. the capabilities and restrictions of linear block Hamming codes

3. the design issues involved in the encoder and decoder stage of an error control codec

4. the basic functionality offered by the QUARTUS II simulation tool  Design and Evaluation of an Error Control Codec Page 3 of 14

TASKS: You are required to complete the following Tasks

Task 1

Design the encoder for a (6,3) Hamming single error correcting codec using the “interleaved” [P1P2D1P3D2D3] format. You can implement your parity generation using XOR gates. Simulate your circuit to check for correct operation.

Task 2

Design the decoder for a (6,3) Hamming single error correcting codec using the “interleaved” [P1P2D1P3D2D3] format. You can use a 3-to-8 line decoder for syndrome decoding and XOR gates for the controlled inversion. Employing an appropriate design, simulate your circuit to check for correct operation.

Task 3

Analyse the performance of the CODEC. Join your encoder to decoder and add an XOR gate with an ‘input’ in each bit transmission line to allow you to introduce errors into the transmission.  Simulate your circuit and check that it can cope with the six single errors as expected.

Task 4

By experimenting with your implemented codec, examine the effect, in terms of additional errors, of (i) all 15 double errors, (ii) all 20 triple errors, (iii) all 15  quadruple errors, (iv) all 6 quintupleerrors, (v) the single sextuple error. Note.You only need consider one of the 8 possible input data words. Why?

Task 5

a) Calculate the post codec probability of a code being in error, A(n), for each of the five categories examined in Task 4.

b) Then calculate the overall number of errors per 6 bit word, Eav, given by the followingmodel based on the binomial distribution as function of the channel bit error probability p,