Circular Delay Memory and XADC Controller Tasks

Task 1 – The Circular Delay Memory

Task 1 – The Circular Delay Memory

Given that the RAM uses 10 address lines, write down the range of addresses in hexadecimal format.

As shown in figure 4a, the ‘Delay’ input is a 10-bit value which is used as the offset between the write and read addresses. Given that the sampling frequency is 10kHz, determine the following:

i. The minimum possible delay between the memory input and output values.
ii. The maximum possible delay between the memory input and output values.
iii. A general expression for the delay in terms of the delay offset and sample interval.

Explain how the memory operates as a continuous circular buffer, i.e. what happens when the write address reaches the highest memory location. Also, consider the situation where the write address is smaller than the delay offset.

Explain how the range of time delays could be increased.

Task 2 – The XADC_Controller

The ‘XADC_Controller’ block shown in figures 1 and 2 is to be based upon that which is used in the workshop examples entitled ‘XADC_Display_RTL_2017.pdf’ (SV) and Ts - Sample TimeRead AddressWrite AddressDelay

‘XADC_Display_BD_2019.pdf’. The ASM chart for the original RTL module is shown in figure 5, the SystemVerilog and Verilog-2001 source descriptions can be obtained from eLearning.

Copy the contents of the ‘XADC_Controller.sv’ into a new text file and name it either ‘XADC_RE_Controller.sv’ (or ‘XADC_RE_Controller.v’, if you are using the block diagram editor tool).

The ASM chart shown in figure 5 requires some modifications and the corresponding source file ‘XADC_RE_Controller’ must also be changed so that the two are consistent.

i. The ASM chart shows that the XADC input signal ‘ADC_Address’ is to be hardwired (connected directly to a constant source) to the value 7’h16. Given that this can be achieved in the top-level design source (either in HDL or block diagram), modify the ‘XADC_RE_Controller’ sv/v source accordingly.

ii. The Vivado Block Diagram Editor requires that the module sources are written in Verilog-HDL rather than SV. Make any changes to the source file to remove any SV language features, such as ‘logic’, ‘enum’ etc. Remember to save the source file as ‘XADC_RE_Controller.v’. (Alternatively, you can modify the Verilog-2001 version of the source provided with example ‘XADC_Display_BD_2019.pdf’)

iii. Modified ‘XADC_RE_Controller’ block. Six new outputs are added to the symbol on the lower right-hand edge. These additional outputs are used by the Block RAM memory, address counter and the output data latch, as shown in figure 3 above. Figure 6 shows a timing diagram defining the timing behaviour of five of the six new outputs, these are all direct outputs that make use of three new states. The ‘rst_addr’ (reset address to zero) output, which is not shown in figure 6, is asserted during the ‘RES’ state as a direct active-high output. Add the new states to the Verilog/SV description of the XADC_RE_Controller module, along with the necessary changes to the module header and parallel statements required to implement functionality shown in figures 6 and 7. Include a complete listing of the module source in your report.