RTL Binary Multiplier System Design: Project Creation, Editing, Simulation, and Implementation

Software and Hardware Resources

• To create a Xilinx Vivado® Project (targeting the Artix-7 FPGA on the Digilent Basys3 development board) and add the provided design, simulation and implementation source descriptions.
• To perform simulations of the design using the Vivado® Simulator and record screen copies of relevant results.
• Synthesise and Implement the multiplier system, capturing screen copies to prove successful design flow.
• Demonstrate the operation of the design using the Basys3 development board, taking images of the board as proof of correct operation. (Subject to access to the hardware)

• Digilent Incorporated ‘Basys3’ Artix-7 FPGA Development Board. Reference Manual.

Supporting Documentation and Files: (available on eLearning portal

At the heart of the system is the 8-bit unsigned binary multiplier (mltp) described as a Register Transfer Level system using the SV hardware description and verification language. The blocks surrounding the ‘mltp’ module provide input values to the multiplier and allow the resulting product to be displayed on the on-board 4-digit, 7-segment display of the Basys3 board. A sliding switch (SW0) selects between displaying the 8-bit input values (Bin and Qin) and the 16-bit product (Prod), all values being displayed in hexadecimal format.

Three push-buttons control the operation of the system, as follows:

i.Start – causes a new multiplication to start, this is pressed after each new test pattern is generated.

ii.Reset – resets the system.

iii.Next_Patt – generates a new random set of input values for Bin and Qin.

Extract all of the source files form the archive provided on eLearning, they are listed above.

Add the source files to the project, grouping them as design, simulation and constraint sources.

Once the files have been added, capture a screen shot of the sources hierarchy from the Project Manager window (you may need to float the window out of the main framework to view all of the sources) making sure that all sources are visible.

Paste a copy of the screen image into your assignment document and add a caption.

Open the SystemVerilog source file for the top-level design source ‘RTL_Multiplier_Display.sv’ and scroll down to the following line:

Change the value of the parameter ‘N’ from 20 to 2, and save the file. Briefly explain why it is necessary to change the value of N prior to simulation of the design.

Explain the meaning of the token ‘.*’, as used in the above line of SV source.

Close the top-level design source and open the source file named ‘Prdgen.sv’ (U10 in figure 1). Study the SV source description and hence sketch a diagram to illustrate the structure of the module.

Use your diagram to explain the operation and purpose of the ‘Prdgen’ module.

Run a behavioural simulation of the design.

When the waveform window appears, delete the traces for the display cathodes and decimal point (CA, CB...CG and DP).

In the Simulation Scope panel, select the ‘DUT’ and add all of the internal signals listed in the Objects panel to the wave window, except ‘q0, q1, q2 and q3’.

Description of the RTL Binary Multiplier System

Select ‘MULT1’ in the Scope panel and add all of the multiplier internal signals to the wave window, except the parameters ‘m’ and ‘n’.

Restart the simulation and save the waveform configuration.

Run the full simulation, until it is automatically stopped by the ‘$stop’ command in the test-module.

Detach and maximise the wave window and zoom out to the full extent of the simulation.

Capture a screen shot of the waveform results and paste/crop into your assignment document, adding a caption.

Zoom in to the waveforms so that a single multiplication operation can be clearly seen (for example between just before the ‘Start’ pulse and after the zero flag (Z) returns to logic-1 and the state returns to ‘T0’.

Capture a screen image of the waveforms and paste them into your assignment document with a suitable caption.

Note down the hexadecimal values of ‘Bin’, ‘Qin’ and the output product. Convert these into unsigned decimal in order to check the validity of the result.

Repeat this for 3 more sets of input values and document using a table.

Zoom in to a selection of the waveforms to show the operation of the multiplexed display, showing both the input values (Bin, Qin) and the Product.

Capture an image of the display control waveforms and briefly explain the operation of the multiplexed 4-digit, 7-segment display.

Close the behavioural simulation tool, saving the waveform configuration file for future use.

Reopen the SystemVerilog source file for the top-level design source ‘RTL_Multiplier_Display.sv’ and scroll down to the following line:

Change the value of the parameter ‘N’ from 2 to 20, and save the file. Briefly explain why it is necessary to change the value of N prior to implementation of the design.

In the Flow Navigator panel under ‘PROGRAM AND DEBUG’ invoke the ‘Generate Bitstream’ process. Click ‘OK’ in any subsequent windows that appear to start the process.

After a short time the process of implementation will complete. Expand the Project Summary panel and capture an image of the lower left hand portion showing the Post-Implementation Utilization statistics for the design in tabular form. Paste a copy of the image into your assignment report and comment on the contents of the table.

In the Flow Navigator panel under ‘IMPLEMENTATION’ expand the ‘Open Implemented Design’ item and click on ‘Schematic’.

This will open a schematic representation of the implemented design, expand this window to fill the screen area and take a copy of the image.

Paste the image into your assignment document, adding a suitable caption.