Learning Outcomes tested in this assessment (from the Module Descriptor):
1. Apply the techniques and methodologies used in the simulation and verification of digital and mixed-signal systems using Hardware Description Languages and create simulation models for verification using appropriate simulation tools
2. Develop their knowledge, skill, and resource and time management applied to advanced design tools and languages in an independent manner.
Academic Conduct: You must adhere to the university regulations on academic conduct. Formal inquiry proceedings will be instigated if there is any suspicion of misconduct or plagiarism in your work. Refer to the University’s regulations on assessment if you are unclear as to the meaning of these terms. The latest copy is available on the university website.
Open the net-list file (.nsx) with the SMASH software and correct any syntax errors that may arise. Select the top-level module and set up a transient analysis to run for 100 us, with a print step of 10 ns. Run the simulation (you may need to click on the run button twice to get the ‘Simulation finished’ message to appear). Add the following waveform traces to the Transient window and zoom out to the full extent:
All analogue traces can be plotted together, the voltage across the storage capacitor can be plotted by including the following text in the ‘.Trace’ command containedin the SMASH pattern file ‘Test_XADC_input.pat’:
Export an image of the full extent of the simulation results shown in the Transient window and insert this into your report, include a suitable caption.
Zoom in to the waveform traces to see the detail around a single ‘cap_sample’ pulse. Estimate the time it takes for the storage capacitor to acquire the sample value. Capture the waveform view and insert it into your report with a suitable caption.
Zoom out to an area enclosing two consecutive ‘cap_sample’ pulses. Use the zoom tool to get a closer view of the vertical change in the voltage across the storage capacitor. Capture the waveform view and insert it into your report, adding a comment suitable caption. Briefly explain the change in the storage capacitor voltage, during the holding interval.
Uncomment resistor R1 in the net-list description of figure 2.1. Given that the required input voltage range of the XADC is 0.0 to 1.0 volts, estimate a suitable value for R1 and rerun the transient simulation. Include the value of resistor R1 in your report. Capture the full extent of the waveform view and insert it into your report, adding a comment and suitable caption.
Specifies the sample interval time as Tsample = 10us. Estimate a suitable value for the low-pass filter capacitor ‘Ca’, in the net-list. For the purposes of estimating the value of Ca, the effect of the XADC input circuitry can be neglected.
Add the capacitor ‘Ca’ to the net-list and rerun the transient simulation. Capture the full extent of the waveform view and insert it into your report, adding a suitable caption. Briefly comment on the effect on the results of inserting the low-pass filter capacitor.
Comment out the sinewave signal source ‘VS1’ and uncomment the pulsed voltage source ‘VP1’. Set the parameters of the ‘vpulse’ module instance as follows (the rise and fall time parameters can be left at their default values):
Copy the instantiation of the ‘vpulse’ module into your report. Re-run the transient simulation and capture the full extent of the waveform view. Export the waveform view and insert the image it into your report, adding a suitable caption. Briefly comment on the effect on the results of changing from a sinusoidal voltage source to a pulsed voltage source.