SystemVerilog Design Assessment - RxSysRTL module

Learning Outcomes tested in this assessment (from the Module Descriptor):

1. Appreciate the need for, and understand the use of system-level design languages such as System-Verilog.

2. Create and implement Register Transfer Level (RTL) designs from system-level specifications, by use of design methodologies, such as Algorithmic State Machines and implement designs using programmable hardware.

3. Develop their knowledge, skill, and resource and time management applied to advanced design tools and languages in an independent manner. Assessment Criteria/Mark Scheme:

You must adhere to the university regulations on academic conduct. Formal inquiry proceedings will be instigated if there is any suspicion of misconduct or plagiarism in your work. Refer to the University’s regulations on assessment if you are unclear as to the meaning of these terms. The latest copy is available on the university website

Objectives:

• To create SystemVerilog (SV) design source descriptions for the various component parts of a Monitoring System comprising an Analogue-to-Digital Converter, Asynchronous Serial Data Transmitter and Receiver along with a display.

• To incorporate an IP (Intellectual Property) module into the design using customisation and interfacing.

• To perform simulations of individual design modules using SV test-modules and the Vivado® Simulator.

• To perform simulations of the complete Monitoring System top-level module using a SV test-module and the Vivado® Simulator.

• Synthesise and Implement the Monitoring System, targeting a Field Programmable Gate Array development board (Artix-7 FPGA on Digilent® Basys3® development board).

• Demonstrate the operation of the FPGA implementation of the Monitoring System using the Basys3® development board by means of a so-called ‘hardwired loop-back’ test.

Task 1 – Create a SV source description of the ‘RxSysRTL’ module

Shows the ASM chart and other details relating to the receiver module ‘RxSysRTL’. The figure shows the behaviour of the module in the form of an ASM chart, along with a symbolic representation and the main internal registers. The internal signal named ‘Start’ is derived from the serial data input ‘RxIn’ such that a single clock-pulse-length pulse is produced on ‘Start’ each time ‘RxIn’ undergoes a logic-1 to logic-0 transition (Refer to figure 3, the ‘MP’ circuit plays a similar role).

At the bottom right hand corner of figure 5, a logic circuit is included to illustrate the operation of the ‘Parity’ error output (parity_error). The system enters state ‘s5’ once a complete serial data character has been received (the shift register (SR) is transferred to the buffer register (BR) in the previous state, ‘s4’) and a logic-1 is transferred to the ‘buffer_full’ output. The ‘buffer_full’ signal enables the parity circuit flip-flop to load a value from the respective logic shown on the diagram (Exclusive-OR and Nand gate).

In the event of a parity error, the ‘parity_error’ output flag remains high until, either a master reset occurs, or the next data character is received The parallel data output of the receiver module ‘data_rx’ is 16-bits in length, in order to drive the 4- digit hexadecimal display logic directly. The data value received from the transmitter occupies the lower bits of this output bus.

The receiver cannot receive another serial data character until the buffer is read, i.e. the ‘read_buffer’ input is asserted.

Using the information provided in appendices A and B, along with create a complete Register Transfer Level (RTL) SV source description for the receiver module, saving it in a text file named ‘RxSysRTL.sv’. The receiver module is to have an identical set of parameter declarations when compared to the transmitter module. The source file can be created within the Xilinx Vivado® software, alternatively Notepad++ could be used.