Assessment on System-Verilog Design and Monitor System Implementation

Learning Outcomes Tested

Learning Outcomes tested in this assessment (from the Module Descriptor):

1. Appreciate the need for, and understand the use of system-level design languages such as System-Verilog.

2. Create and implement Register Transfer Level (RTL) designs from system-level specifications, by use of design methodologies, such as Algorithmic State  Machines and implement designs using programmable hardware.

3. Develop their knowledge, skill, and resource and time management applied to advanced design tools and languages in an independent manner.

Assessment Criteria/Mark Scheme:

You must adhere to the university regulations on academic conduct. Formal inquiry proceedings will be instigated if there is any suspicion of misconduct or plagiarism in your work. Refer to the University’s regulations on assessment if you are unclear as to the meaning of these terms. The latest copy is available on the university website.

Objectives:

• To create SystemVerilog (SV) design source descriptions for the various component parts of a Monitoring System comprising an Analogue-to-Digital Converter, Asynchronous Serial Data Transmitter and Receiver along with a display.

• To incorporate an IP (Intellectual Property) module into the design using customisation and interfacing.

• To perform simulations of individual design modules using SV test-modules and the Vivado® Simulator.

• To perform simulations of the complete Monitoring System top-level module using a SV test-module and the Vivado® Simulator.

• Synthesise and Implement the Monitoring System, targeting a Field Programmable Gate Array development board (Artix-7 FPGA on Digilent® Basys3® development board).

• Demonstrate the operation of the FPGA implementation of the Monitoring System using the Basys3 development board by means of a so-called ‘hardwired loop-back’ test.

At the bottom right hand corner of figure 5, a logic circuit is included to illustrate the operation of the ‘Parity’ error output (parity_error). The system enters state ‘s5’ once a complete serial data character has been received (the shift register (SR) is transferred to the buffer register (BR) in the previous state, ‘s4’) and a logic-1 is transferred to the ‘buffer_full’ output. The ‘buffer_full’ signal enables the parity circuit flip-flop to load a value from the respective logic shown on the diagram.

In the event of a parity error, the ‘parity_error’ output flag remains high until, either a master reset occurs, or the next data character is received

The parallel data output of the receiver module ‘data_rx’ is 16-bits in length, in order to drive the 4- digit hexadecimal display logic directly. The data value received from the transmitter occupies the lower bits of this output bus.

Capture and paste an image of the full extent of the simulation waveforms into your report, ensuring all top-level and added internal signal names are legible at the left-hand side. Add a suitable caption to the image and comment on the results.

Zoom in to the waveforms in order to enclose a single data character (between two consecutive ‘write’ pulses).

Capture and paste an image of the single character waveforms into your report, ensuring all toplevel and added internal signal names are legible at the left-hand side. Add a suitable caption to the image. Confirm that the data value appearing at the ‘data_rx’ port, coincident with the assertion of the ‘buffer_full’ receiver output, matches the value applied to the ‘data’ port of the transmitter, during the ‘write’ operation.

Pan across the waveforms to check that each value transmitted is correctly received by the ‘RxSysRTL’ module correctly.

Zoom in to the waveforms to enclose an individual data bit (1 or 0). The values of the internal states and counters should be readable (set radix to unsigned decimal for the latter). Place the cursor on the waveform to show at what point the receiver shift register is loaded with the value present on ‘RxIn’.

Capture and paste an image of the waveforms into your report, ensuring all top-level and added internal signal names are legible at the left-hand side. Add a suitable caption to the image. Measure the width of the data-bit using the cursors and markers in the wave window, comment on the value recorded.

Modify the source descriptions of the test-module and/or DUT to demonstrate the correct behaviour of the ‘parity_error’ output of the receiver. Capture appropriate waveforms and document the changes made to the sources. Briefly explain the operation of the parity error circuit