Laboratory Examination on Design of Current Mirror and Differential Amplifier using Cadence OrCAD So

Learning Outcomes on the Module Descriptor

You may use any of the material from the simulation files as needed to solve this examination

PLEASE NOTE: You should only answer the number of questions required above. If you answer more than this, your answers will be marked in the order they appear in your answer sheets, up to and including the required number. Any additional answers will not be marked. Please cross out any work that you do not wish the marker to consider. Please check your work to ensure you have answered the correct number of questions and they are clearly numbered. You must abide by the University’s regulations on academic misconduct. Formal enquiry proceedings will be instigated if there is any suspicion of misconduct in your work.

Learning outcomes on the Module Descriptor:

1. Pertinent design knowledge from relevant research for complex analogue abstractions. (UK-Spec 3rd Ed. SM1m, SM1fl)

2. Critically evaluate advanced design concepts for the design of analogue circuits, at pertinent abstraction levels. (UK-Spec 3rd Ed. EA2m, EA1fl)

3. Demonstrate expertise in the use of industry standard CAD tools for the design, testing and modelling of innovative analogue circuitry. (UK-Spec 3rd Ed. EP3m, EP3fl D4m, D3fl EA3m, EA3fl, EP9m)

4. Evaluate a design for a relevant audience in the context of professional, & commercial standards. (UK-Spec 3rd Ed. D6m, ET5m, ET5fl) Specific interpretation of the Learning Outcomes with respect to this laboratory examination.

This design focussed examination is based on the Cadence OrCAD software. The examination is a problem-based assessment talking the application of knowledge and understanding to both the design process and the practical skills of CAD tool usage. Critical comparison of circuit topologies will be performed using the CAD tool and an advanced use of simulation.

This examination has a number of questions that lead to a larger design, theses should be tackled linearly. Simulations will be used extensively in this paper, you therefore need to understand and use the CAD tool appropriately; you need to provide screen captures of relevant results in your answers.

Where you are asked to explain a result please ensure you provide a comprehensive answer. Marks are as noted broken down in each question.

Key transistor parameters for use in this design are:

The following specification is to be achieved:

• Supply Voltage = +/- 9V (dual rail current mirror therefore 18V)

• Ireference (ICQ1) = 1mA

• Effective Early Voltage = 10*VAF

• Ioutput (ICQ3, ICQ4) = 2mA

Make clear your equations and calculated values of resistors Rref, Rdeg1, Rdeg2, Rdeg3.

Make clear your optimised values after simulation.

Explain why the Beta helper current mirror is used in designs so often, what are the key advantages of this design compared to a basic mirror with no beta helper transistor. You may think about counting base currents to demonstrate your explanation.

Using your design of current mirror from Q1; you are to assess the performance of your current mirror against Temperature. Use the temperature range from 0 to 100 ºC to assess the performance of the Current Mirror design.

Simulate the circuit:

• How does the Reference current (ICQ1) move with temperature?

• How the Voltage labelled VRef move with temperature?

• Ensure your simulation works correctly adjusting RelTol in advanced options as necessary.

Explain (where appropriate using equations) how temperature has affected the design of the current mirror reference current, output current and the voltage reference voltage Vref.

Q3 Design a differential amplifier, and implement two of them in place of the resistors RLOAD1 and RLOAD 2 in the current source from Q1.

The specification of the differential amplifiers are the same and listed below:

• Supply Voltage +/- 9V (Dual supply rail),

• Tail currents ICQ3 and ICQ4 = 2mA (from Q1),

• ADM = 100 differential gain for both amplifiers,

• Vin Differential 10mV @ 1kHz (VinA, VinB),

• Vin Common 1000mV @ 1 kHz (VinC),

• Differential 1 replaces RLOAD1 and will measure ACM,

• Differential 2 replaces RLAOD2 and will measure ADM.

Make clear your design equations for the values of RC1, RC2, RC3 and RC4 using the small signal equivalent model to derive the gain equation for ADM. All the resistors will have the same value as this is a balanced design.

Determine the value of gain ADM from simulation and then optimise the values for all RC resistors to ensure a precise ADM gain value of 100.

Explain the limitation of the output signal swing from this design in relation to the power supply provided (dual rail +/-9V). What would have been a better design structure for this type of gain requirement?