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Lab 3b: Memory Lab | Lab 3c: Optional I/O (Extra Credit)

Lab 3b: Memory Lab

The CPU lab will consist of two or four questions regarding memory system features and is worth 50 of the 250 points total for this lab. The questions in this lab will come from material and will be about virtual memory and cache systems. These questions will be very similar in feel to the floating point questions in Lab 2. In other words, they will not be design questions, rather, they will help you to develop your understanding of how virtual memory systems and cache work.

  1. Problem 8.8 in your book
  1. Problem 8.10 in your book
  1. Problem 8.14 in your book

This optional, extra credit, portion of the assignment will be made available in the final week. You can expect it to be worth about 10% additional credit for the Lab and that it will involve I/O. If I have the time, this will be an add-on for your CPU, if I cannot get that completed in time, then it will involve one or two questions from chapter 9 that will ask you to discuss design changes to your CPU, but you will not be required to implement those changes.

1. For this Optional I/O lab worth an additional 25 points Extra Credit, you must build a 16 bit signed decimal display unit that displays numbers written to memory location 0xFFFF. Note, because of the signed immediate extension, this means that you only need to write the number to be displayed to 0xFFF and the sign extension will take care of the rest. This display should continue to display the number written until a new number is written to the address. You may use any element in Logisim.

2. For this exercise I suggest you break the design into two sub-circuits.

a. The first sub-circuit takes a sixteen bit two's complement number in and provides outputs for each of the five decimal digits and sign. You should be able to test this independently of your CPU.

b. The second sub-circuit connects to Clk, Reset, the DMAddress and the DMData and provides the 16 bit I/O port at address 0xFFFF. Note for this to work the DMData should be connected to DMDataIN inside of your CPU. It was previously connected to DMDataOut in my examples.

c. Write a short program to write the number -4242 in decimal on the display. Include your assembler and machine language code in your writeup.

d. If your circuit is working correctly, the example program from above will write the sequence of numbers to the decimal display.

Lab 3c: Optional I/O (Extra Credit)

e. Adding a HEX display directly to the I/O port as shown below will help you with any necessary debugging.

3. If you do this portion of the lab you must include the decimal display in your video when you run the example program provided above.

The primary task of this lab is the design and construction of a simulated CPU in Logisim. You will be building a version of mARMI, the minimal ARMish CPU. Take a look at Appendix 1 for a detailed description of the mARMi CPU. 

For this lab you will be required to use version 2.15 of Logisim Evolution. This Is to maintain compatibility with grading scripts should my graders need to use them, and/or, to ensure that my graders can load your file without error. There will be some additional strict requirements regarding the shell files that are given to you. You may not rename any ports or modules that are provided. You may also not move them arootThey are provided with Tunnels so that you do not need to move them around. Cro not add any additional pins to the tootel module or the CPU module. You may download V2.15 of Logisim Evolution from the following link. 

If you have questions about using a jar file to run Java application, your TAs will be able to help you get things sorted. 

V002 - Updated the register file, corrected some typos, documented the bit width of shifts, fixed FOR mnemonic.

V001 - Initial Release.

You have been provided with a Logisim file that provides the front panel shown above along with the Implemented front panel controller. This controller will allow you to step through instructions, nen the CPU, and reset the CPU. You are also provided with the ROM that is the instruction memory on the front panel. The reason for putting the ROMoutside of the CPU is to make loading programs less tedious. You have been provided with an empty shell for the CPU module. Building this module is your task for this lab. 

Our focus In this lab is in building a CPU and understanding the deal involved. Consequently, you are not restrkted to using simple logk gates. You may use many of the powerful features available In Logisim Evolution 2.IS. Do not worry about minimization of gates, rat her, focus on building a reliable CPU and understanding the relationsNp between programming and CPU architecture. 


Full sub mission details will be provided on Canvas. However, you can expect three things with this project. First, you must do a writeup, second, you must submit a tiro file created and edited only with Logisim Evolution version 2.15, and third, you will be creating a short (two minute mac runtime of you demonstrating the operation of your CPU. 

Your first task is to build out the Instruction fetch unit. The insmection fetch unit is responsible for fetching the net Instruction to execute. Figure 72 in your book gives you a rough outline of the functionality of this module. The IMP input shown here is, in essence, the PCSet controller output shown In figure 78. This line goes high whenever the CPU is executing some kind of branch.

The jump address to be loaded into the program counter is provided via the WBBus Input Since this unit will contain the program counter register, it is essential that it be connected to the system- wkie Reset and Clk signak. Ibis way, when you reset the CPU, the program counter will reset to zero.

While building this it's important to keep some details in maxi. A real ARMCPU uses byte aligned memory and 32-bit data words. This means that the next instruction Is at PQ4. Were using word-aligned memory with 16-bit words. So, for us, the next Instruction is at the next location in memory. Also, in ARM, RLS, which is the PC register, always holds PC+13, or two Instructions ahead. Your book mentions that this is for historical reasons. Consequently, our last righter, R7, will always point to the next Instruction to be executed, PC4.1. This is why we have a PCPIus1 output.

Note that we must provide the instruction memory address to the memory that is outside of the CPU via the IMAddress pin. 
If you build this unit cwrectly, you should be able to step through memory full of zeros and see the Instruction memory inaease by one on every step. You should see the contentsof the Instruction memory on the Instruction memory data display. Pressing reset should retwn the Instruction memory address to zero. 

You are very close at this point to property Implementing the NOP and HALT instructions, but don't gm ahead of yourself, build some more stuff working first and then come back to these a bit later. 

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