Midterm Project for MSDAP Application using HDL

Input files are posted on eLearning, which includes
(a) data1.in & data1.out
(b) data2.in

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The Midterm project aims to build a behavior model for MSDAP application by using Hardware Description Language (HDL). The combination of homework 6 and homework 7 should give you a good shape of this project. You may review the description of homework 6 and homework 7. The system diagram is shown as following.

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Each group will one specific I/O setting in the mid-term project. The settings assigned to you contains the following aspects:
1. Input data transition format: serial / parallel
For simplicity, in HW6 we don�t limit the transition format. If the inputs are serial, it takes 16 �Dclk� cycles to transfer one data. (See the following timing diagram)

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However, we can choose a 16 bit data bus as input, with witch the input data can be transferred within 1 �Dclk � as follows.

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For simplification purpose, we don�t change the frequency of �DClk�. Then you will have 15 �idle� cycles before next frames of data.

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2. Output data transition format: serial / parallel
For output, we can also use the either serial ports or parallel ports. Serial outputs would be like the following:

Parallel outputs would be:

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Please note for parallel, we also have some �idle� cycles during which there is no change with the output port.

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3. �Start� signal: high / low enable
4. �Reset� signal: high / low enable
5. �Frame� signal: high / low enable

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For the consistency of IO pins, you should declare a 16-bit input port and a 40-bit output port. If the data is transmitted in serial way, only one bit is used.

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I/O settings will randomly be assigned to each group in the lecture. Please strictly follow your I/O settings to finish the design.

�Reset� behavior of your module depends on when it is received, as shown in above figure.
For the testing purpose, �reset� is assumed to be sent in the first half of �frame�. In this way, you should discard current frame, and set outputs to be zero. (You should include this assumption in your spec)

As a real-time audio processing AISC, the length of data inputs to your design is infinity. In this case, you cannot assume the total length of the inputs. In the midterm project, your design is restricted to use the following memories.
1. The Rj memory: 16bits x 16 (number of Rj) x 2 (channels)
2. The coefficients memory: 16bits x 512 (number of coefficient) x 2 (channels)
3. The data memory: 16bits x 256 (filter order) x 2 (channels)
4. You can use necessary registers to store the intermediate results (like the �u�). However, the number of such register should be at most 40bit x 16 (number of u) x 2 (channels).

You might allocate a small amount more registers if you need internal signals to complete the operations. However, allocating a large block of memory to hold all data at once is prohibited.

800 consecutive 16bits-Zeros for both channels will force the chip entering sleeping mode. Non-zero value detected from either channel will awake the chip.

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1.Write a well-organized specification for MSDAP (20%). The Spec. should at least cover the followings topics.

(1.1) Description of MSDAP algorithm. Give an example of convolution. (Do not use the example in homework) (2%)

(1.2) Pin settings for MSDAP Chip (2%)

(1.3) Operation modes (descriptions of FSM) (2%)

(1.4) Input/Output signal formats (clearly explain the I/O settings assigned to your group) (4%)

(1.5) The frequency of �SCLK� and how you determine it. (10%)�

(2.1) Generate the input signals whose format matched with the Spec. (15%) (2.2) Collect outputs from MSDAP chip and generate the output file. (15%)

(2.2) Collect outputs from MSDAP chip and generate the output file. (15%)

Note* Test files can be found on eLearning. In midterm project, all Rjs, coefficients and data are in the same file. Please parser them in your testbench. There are two sets of input, data1.in and data2.in. data1.in is with the reference output file data1.out for the test purpose. And the other one, data2.in is used to generate the output of the submission. The occurrences of reset are marked in comment section of the input file.

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(3.1) Generate the output signals whose formats matched with the Spec. (10%).

(3.2) Implement the Finite State Machine (FSM) whose state transitions matched with the Spec. (10%)

(3.3) Generate correct output. Simulate your design with modelSim and demonstrate how your design follow the spec. with waveform (20%)

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Note: You will lose points if you design violates (3.3). And the following violations will cause you lose all points of (3.3)

1. Use multiplication in the computation.

2. Store all input data then compute the output.

(4.1) Write in logical, formal and technical manner.

(4.2) Include waveformsfigurestables to justify your design.

(4.3) Report (5%).