MIPS Design: Addressing Modes, RISC Architecture, and Data Hazard

Problem 1: Five Addressing Modes of MIPS Design and RISC Architecture

Problem 1:
What are the five addressing modes of the MIPS design? 

Write a concise essay to convince your readers that those five addressing modes represent the architecture of the MIPS processor? 
Suppose you are a sales engineer who needs to promote (sell) the Reduced Instruction Set Computer (RISC) to an executive (who has little patience). In this problem, you need to come up with a sales pitch of 50 words or less (that means you need to figure out the key selling point of RISC).

Problem 2:
Modify the given machine below so that it supports the jr  (i.e., jump register) instruction. You need to make your final modification directly on the given diagram

You may use the space below to show your in-between work or explanation: 

Problem 3:

Given three instructions below:
Or $6, $4, $7
Sub $2, $1, $3
And $12, $2, $5

Modify the pipeline machine below (by adding the forwarding related lines and components)  so that it can resolve the above data hazard of the third instruction (and $12, $2, $5). Please note that your modification should be just enough to resolve the given data hazard. Any additional modification (i.e., it does not involve the above data hazard) will result in a penalty.