Designing Control and Block Register for ALU Machine 4-bit

Objective

In this exercise we will design Control, a simple state machine that controls ALU_machine_4_bit. Block Register will also be designed. This lab will be completed individually.

Register and Control – Block Level Verification

In this step a test plan for Register and Control will be written, the test-bench will be designed, and the test plan will be executed. You may perform each of these steps once if you consider Register and Control a system or twice if you consider them separately.

i. Test Plan Development

Write a test plan that specifies the functional features that are to be tested and how they will be tested. Be sure that for every state in block Control you test all entry and exit paths. Test a range of values for input Data.

ii. Testbench Development

Using the test plan, write a test-bench that verifies the functionality of blocks Register and Control. To make the test-bench self-checking predict the expected result and flag an error if the expected result does not match the actual result.

iii. Test Execution and Model Verification

Using the test-bench developed in ii. Testbench Development, implement the test plan written in i.

Test Plan Development