Design, Simulate, Implement, and Demonstrate a Parallel I/O Chip (PIO) using Xilinx Artix-7 FPGA

About Parallel I/O Chip (PIO)

Design , simulate, implement, and demonstrate a Parallel I/O chip (PIO) specified below. Use one Xilinx Artix-7 FPGA chip (the chip that is actually mounted on your Nexys A7 Board), DIP-switches, bounce-free switches, Bar-LED modules, and various buffer chips, as needed. The states of the input signals are to be set by switches, and outputs are to be displayed using LEDs. The switches representing microprocessor data output signals should be separated from the PIO's Three-State (TS), bi-directional bus signals by a TS buffer chip. The LEDs should be driven by inverting-output buffers to provide for a true display of the status of the signals. You must provide for your own parts. 

Functionally, this PIO can be viewed as a segment of the Intel i82C55A chip (refer to Intel's Web site, or any recent Intel Peripheral Components Handbook for further readings). The microprocessor interface signals are as follows: CE*, A0, RD*, WR*, RESET, and INTR (* stands for active-low), as well as D0, ..., D7 (bi-directional TS data bus lines). On the peripheral interface, just one 8-bit data input port P0, ..., P7 should be implemented along with supporting hand-shake signals STB*, and IBF. The key control signals of the PIO chip (CE*, RD*, WR*, and STB*) should be driven by bounce-free switches. 

The register model of your PIO chip consists of three registers: Data_In (selected by A0 

• 0, for read access only),Control_Reg (A0 = 1, for write access only), and Status_Reg (A0 = 1, for read access only). These registers are accessed while both

CE* and the required control signal (RD*, or WR*, respectively) are asserted along with the particular value of A0 as specified above. 

The bit maps of these registers and their functions are as follows: 

Control_Reg.0: MODE Bit 

if 0: Mode 0 input from peripheral 

if 1: Mode 1 input from peripheral 

Control_Reg.1: INTE (Interrupt Enable) Bit 

if 1: signal INTR is enabled 

if 0: INTR is disabled 

Status_Reg.0: IBF (Input Buffer Full) Bit 

Status_Reg.1: INTE (Interrupt Enable) Bit 

Status_Reg.2: INTR (Interrupt Request) Bit 

Signal RESET resets all control and status register bits, and the INTR signal to 0 when it is asserted. RESET is active-high. In Mode 0, Bit Control_Reg.1 is irrelevant and the Status_Reg is not available (not supported). 

The basic timing diagrams for the peripheral and microprocessor interface signals are given on Page 3. You are NOT required to implement the exact delay times given in the i82C55A Data Sheets, but you are responsible for the antecedent - consequent relationship between handshake pairs of signals. For your orientation, research the Xilinx Web site for information on the Artix-7 chips. A link is provided in the Data Sheets Section of the Class Web Page. 

1. Give a narrative summaryalong with a detailed schematic diagram of your circuit. In the schematics, represent the Artix-7 chip by a rectangular block with signal names assigned to the appropriate pins of the Pmod Headers. Also show the detailed design steps (i.e., primitive flow map, reduced state table, assigned state table, logic functions) for the asynchronous sequential logic section of your circuit along with your comments.
   
   
2. Design, simulate and implement the circuits that should be mapped to yourArtix-7 FPGA. You should design your circuits in VHDL and use the current Xilinx Vivado and Mentor Graphics ModelSim tools to implement your chip. You should also carry out post-route simulations using .do files to evaluate the real-time performance of your design.

Comment on your simulation results. Submit electronic copies of your .vhd, .xdc and .do files, your simulation timing diagrams with comments, as well as the top page of the Project Summary Report.

1. Download your.bit file to the Artix-7 chip on your Nexys A7 Board. Hook up the board to the rest of your circuit you have built on your Breadboard.

Use short videoclips to demonstrate its correct operation.

1. Submit your Project Reportas a single .pdf file through the appropriate Drop Box in Elearning. You should also submit your recorded video clips in the Drop