Tradeoff Between Power Consumption And Processor Performance In Wearable Devices

Requirements
• Demonstrate an understanding of Operating System concepts; processes, shared memory, concurrency file systems or performance processing
• Demonstrate you are able to conduct scientific research
• Demonstrate you are able to critically analyse several sources of information on a topic

Topic outcomes achieved
• The aim of the assignment is to provide you with an opportunity to apply your new knowledge of operating system concepts
• Demonstrate a working knowledge of operating systems concepts
• Demonstrate you can analyse published academic research and present an argument

Voltage Scaling

The bulky portable computers have been facing replacement by small wearable in the current technology. The wearable devices have introduced several challenges that are very much significant and different from the traditional models of computer. In the present set up the available wearables have long battery life, low weight and advanced functionality. The main goal of the next generation is possibly to extend the services beyond mere emails, limited computation and voices(Danowitz et al 2014).

 The power consumption has become a limiting factor for the functionality of the services of the wearable devices. This has been the case despite the fact that there has been advances in the technology. Lowering  the voltage supply normally requires that the components involved are operating at a very low voltage. Additional reductions can be handled through selective lowering of the voltage of the input. This particular paper investigates the connection or the tradeoff that exist between the power consumption and the processors performances.  As opposed to the previous studies or relevant projects on the same task that have been relying on the processes of simulation, the study has realized the practical implementation that is installed as part of the computer. This particular feature allows for the  presentation of the best  measurement of the results in the voltage scaling. The potential gain in system can be obtained from the illustrated numbers.

Voltage Scaling

In this particular section ,there is introduction of the basic principles that are behind the consumption of power and the voltage scaling effects. For cases of the digital circuits of CMOS,moderation of the power consumption is possible. Majority of the microprocessors employs the use of digital CMOS.Such circuits have both static and dynamic power consumption. The causes of the static power consumptions include leakage and bias currents. This effect however is insignificant in the cases of the designs that consume more than ImW of power. The dynamic component is the dominant power consumption through  dynamic system of the CMOS microprocessors(Macias et al 2012). The power is consumed by every transition of a digital circuit. The dynamic power consumption is equivalent to

Dynamic = X M k=1; Ck   V 2 DD in which M is the number of gates in the circuit, Ck is the load capacitance of the circuit gate.

 In order to put the above formula in use, the relation that exist in the voltage, frequency and power consumption must be known. It is very interesting that the specification focuses on the constraints that are very practical. At the lowest frequency which is normally at 200MHz,the

Embedded Platform

processor operates at 29% of the highest speed. This speed translates to less than 13% of the maximum power. If the voltage scaling would not have been present, the scaling of power would have been more than 13/29.This particular result may look better but it is important to note that the system performance has not improved at all.

 In the analysis of the process, the benefits of the system are to be weighed against the consumed power within the remainder of time. In a wearable system, the power consumption is an obvious cost measure. This is because the amount of energy that can effectively be carried in the batteries is known. The bitter challenge is that most batteries do not operate efficiently when the power demands has reached high peaks. The peak periods occur when the microprocessors are switched on and off frequently. An equal demand of power that is distributed evenly increases the life of the battery by almost 25%.It is therefore recommended that switching off the clock is better than putting on the sleep mode(Kawai and Amano  2012).

The study of voltage scaling has been achieved through the process of simulation. The process of simulation is known to be very promising hence the time has validated the operation to be at 1.5V according to the provided datasheet. It is very common to note failed cases whenever the operations are performed outside the specifications. The conducted experiments indicate that the feasible range of voltage is between 0.8V to  2.0 V(Mori et al 2014).

The embedded platform has got very strong ARM processor that has been displayed in the board below(DIG).The board that is apparently called LART has got a size of 7.5x10cm and weight of 50gr.The memory capacity is at 32MB for volatile and 4MB for the nonvolatile memory.LART has a programmable memory that has been installed to the voltage regulator. The sample (LART) runs under a control of the Linux operating system whose version is 2.2.1.2.This system has been modified and also structured to support the voltage scaling and frequency as well. The  model of kennel has been added to change the frequency of the clock and also to recalibrates the internal relay routines(Macias et al 2012).

The most targeted relays are those which have busy- wait when counting the instruction cycles. The module of kernel assist in the adjustment of the kenel.The code has been instructed in such a way that it can be interrupted  regularly and also does not depend on the external memory. This memory may not be available all the way through.

Results

In order to measure the power consumption of the system of LART,the configuration that has been shown below was used. The power of the battery that is not regulated is converted into a mode that is fixed to 3,3v for all the included components. A variable regulator is used in the supply of the processor voltage. The accuracy of the component is at 2%.

Results

The section normally describes the effects of the voltage scaling and also frequency. These parameters affect the performance of the memory and the processor performance. Several bench marks can be run as well as the full blown. In the process of the run, the voltage and frequency were kept constant(Sun et al 2015).

Required voltage

In the first experiment for the determination of the frequency of each clock was at the minimum required voltage The decoder that was used was rated at the H-263 in order to check if the processor was operating at the required frequency and also at the proper combination of the voltage. The best recommended frequency at which the operations of the system was at the minimum energy consumption was 59MHz.At this particular frequency, the voltage was at 0.79V.The voltage scaling really contributed and the consumed frequency was at 1/5 of the required instruction of the peak performance.

The followed experiment was to check on the impacts of the voltage scaling that is on the power consumed. The power consumption was done under two different loads that was in the idle and cpu intensive. The background power consumption was determined using the idle mode. Such power consumption will always take place regardless of the load on the processor. The scheduler of Linux will always subject the system automatically into a sleeping mode when the processor is not active. In the idle mode, the CPU clock is stalled while other components remain operational including the memory controller(Toprak et al 2014).

All these services are normally driven by the clock of the processor. This probably explains why the consumption of power in the mode that is idle will increase as the frequency increases. The component of SA-1100 normally support the sleep mode very efficiently although this mode tend to interrupt the transfer of DMA and also stop the LCD controller that is known to block the access of the memory available(Wagschal et al 2012).

The cpu-intensive loads is normally made of an exercise of benchmarking within the CPU and also the cache that operates on the variable voltage of the core. The first measurement was taken when the voltage was kept constant at 1.5V.At this particular voltage, the power consumption increases linearly with the increase in the frequency. This was as per the expectation. The next measurement was done when the power voltage was set at the minimal value. The curve that was obtained was a clear indication of the quadratic increase of the power as tHE frequency increases.

The extent to which power consumption is affected by the memory is normally difficult to predict. This is because the operation of the memory is always at the voltage of 3.3 while the operation of the processor is at variable voltages. The sample of LART that was used normally operate at 32MB of the EDO-DRAM. The time for access is at 60ns.There is need of the imbech to be used in the measurement of the power consumption.

 This is done while performing random reading from the memory which is known to be circumventing the cache. The power consumption will include the voltage scaling. The timing of the memory must be programmed through specification of the sequence of the bit that is used in the clock sequencing. It is important to note that the combination of the bandwidth and consumption of power normally show a relative cost to each other(Wegert et al 2015).

The amount of energy that can be saved by making the applications dormant or active will always depend on the ability of the support system to follow the changes that are in demand. The assessment of the responsiveness included the addition of the scaling of the voltage to the module of kernel. The module could set the input never the frequency changed. This was possible even at the minimum level’s digital oscilloscope is needed to measure the required time to alter the new frequency voltage parameters. The recommended time difference should be at 140us.This time is very insensitive to the frequencies and should be stabilized in the internal clock(Zhang et al 2012).

Conclusion

Power consumption is the well-known limiting factor for the operation of the devices of wearibles.The matching of the performance variables should be done accordingly considering that the interactive applications that include wireless communications generates a burst of activities.

References

Danowitz, A., Kelley, K., Mao, J., Stevenson, J.P. and Horowitz, M., 2012. CPU DB: recording microprocessor history. Queue, 10(4), p.10.

Kawai, S. and Amano, A., 2012. BRCA1 regulates microRNA biogenesis via the DROSHA microprocessor complex. J Cell Biol, pp.jcb-201110008.

Macias, S., Plass, M., Stajuda, A., Michlewski, G., Eyras, E. and Cáceres, J.F., 2012. DGCR8 HITS-CLIP reveals novel functions for the Microprocessor. Nature structural & molecular biology, 19(8), p.760.

Mori, M., Triboulet, R., Mohseni, M., Schlegelmilch, K., Shrestha, K., Camargo, F.D. and Gregory, R.I., 2014. Hippo signaling regulates microprocessor and links cell-density-dependent miRNA biogenesis to cancer. Cell, 156(5), pp.893-906.

Sun, C., Wade, M.T., Lee, Y., Orcutt, J.S., Alloatti, L., Georgas, M.S., Waterman, A.S., Shainline, J.M., Avizienis, R.R., Lin, S. and Moss, B.R., 2015. Single-chip microprocessor that communicates directly using light. Nature, 528(7583), p.534.

Toprak-Deniz, Z., Sperling, M., Bulzacchelli, J., Still, G., Kruse, R., Kim, S., Boerstler, D., Gloekler, T., Robertazzi, R., Stawiasz, K. and Diemoz, T., 2014, February. 5.2 distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8 TM microprocessor. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International (pp. 98-99). IEEE.

Wagschal, A., Rousset, E., Basavarajaiah, P., Contreras, X., Harwig, A., Laurent-Chabalier, S., Nakamura, M., Chen, X., Zhang, K., Meziane, O. and Boyer, F., 2012. Microprocessor, Setx, Xrn2, and Rrp6 co-operate to induce premature termination of transcription by RNAPII. Cell, 150(6), pp.1147-1157.

Wegert, J., Ishaque, N., Vardapour, R., Geörg, C., Gu, Z., Bieg, M., Ziegler, B., Bausenwein, S., Nourkami, N., Ludwig, N. and Keller, A., 2015. Mutations in the SIX1/2 pathway and the DROSHA/DGCR8 miRNA microprocessor complex underlie high-risk blastemal type Wilms tumors. Cancer cell, 27(2), pp.298-311.

Zhang, Y., Lu, P.Y. and Chen, Y., Broadcom Corp, 2012. Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems. U.S. Patent 8,335,960.